The present invention relates generally to memory devices and in particular to the circuit design, device design, and processing technology of the high speed, high density, and low power physical constructs for memory cores, IO data buffer arrays, and control blocks.
Conventional high speed and low power buffer storage systems have evolved over time. FIG. 1 illustrates a first generation buffer storage system 10. There are 2 NFET pass transistors and 2 CFET, which formed a latch. The system 10 uses no pull-up transistors for the latch portion of the cell. The problem with this type of system is that it was slow and unreliable to hold information. FIG. 2 is a second-generation buffer storage system 30. In this system 30 the SRAM cell using high value resistor pull up. The resistor consumes DC current, and is slow when a large array capacity is involved. As the density gets higher, it consumes large DC current and the circuit is slow. FIG. 3 is a third generation buffer storage system 50 which uses thin-film Poly PFET (TFT) as active pull-ups. The TFT is attractive as the PFET and intra circuit connecting stacked in vertical space, hence the cell elements overlaps in the horizontal dimension yielding smallest bulk area. But like its predecessors, it is also slow, and suffers from leakage. FIG. 4 is the latest generation of conventional buffer storage systems 70. The system 70 uses 2 bulk PFET as pull-up in the latch portion of the cell. The problems with this type of system are large cell area, and it is difficult to scale down in operating voltage because of fixed high VT in the CFET.
The more recent configuration uses the topology of 6 transistor cell. All of them are in the Si bulk. The cell size is bulky, but it has been successfully implemented with the latest CFET 0.15 um technology as photolithographic rules for layout.
It is important to realize that the IC cost is closely related to the horizontal cell size as one wishes fit more dice in a wafer. The cell pitches in each cell dimensions are related to the length of the bit lines and word lines hence to the array sizes. The capacitances associated with every main circuit element intra and/or inter cell wise play an important role in speed considerations, and the noise margins are often compromised by the designers with speed in conjunction with the dc/ac power consumptions in the determination of Vcc supply, and signal and acceptable noise levels.
Accordingly, what is needed is a buffer storage system, which overcomes the above-identified problems. The present invention addresses such a need.
An improved buffer storage cell configuration is disclosed. The buffer storage cell comprises four (4) CFET and two (2) Schottky diodes. It is suitable for voltage and physical scale-down and is inherently superior to the conventional six transistor (6T) SRAM cell. This device can be utilized to minimize area and power, increase speed and improve reliability.
The cell can be a basic circuit element to form a core or can be utilized in arrays for various applications. The cell can be a standalone memory product or can be mixed with other products in the System On a Chip (SOC) environment. Applicable categories of commercial products include but are not limited to SRAM, DRAM, Flash, CAM, PLD and ASIC controllers or micro-processors.
A cell configuration in accordance with the present invention is compatible with existing CFET/BiCFET, GaAs, or SiGe processes, which means it has the least entrance barrier for its acceptance by the foundries and to the system users. The 2-Diode and 4 CFET FET structure can be extended to include a PN junction diode where the device is totally insulated without utilizing biasing wells.
A system and method in accordance with the present invention provides for an efficient solution for data storage and access. The constructs can be in the form of standard IC commodities of any organization, which contains the arrays employing the cells and/or techniques in accordance with the present invention.
Still other fields of possible functional uses include but not limited to the buffer units of all main stream emerging IC products in digital telecommunication equipment, wire or wireless Telephony devices, CPU and disk cache, Digital Signal Processors (DSP). It can be used in CFET, BiCFET, GaAs, or SiGe processes or any compatible technology.
The means of providing various cost-performance memory solutions are many. For any system, the speed grade ranges from low to high are, Disk devices with search time in mS, Flash device read/write in uS, DRAM in 50 nS, and SRAM in near ns, 16 Mb of xc3x9716 configuration, i.e. 1Mxc3x9716, in 2-5 nS. It is always critical to provide options to a system designer with the basic memory cell and organizations of various high speed, low area, and low power to fit ones system unit application. In the digital RAM domain of semiconductor devices including DRAM, Flash, and SRAM, the trend is to scale down the physical size of the cells on chip, operating voltage and currents are less for each generation of advanced solutions.
A more efficient circuit means has been proposed as viable approach to implement control logics with Diode Transistor Logic. Previously in the 1980s, DTL was once the backbone technology in Bipolar transistors. This invention teaches concepts to realize control functions and levels by various CFET and SBD configurations in additional to Buffer cell applications. Therefore is cost-performance attractive as a generic logic and memory tool-box suitable for any SOC applications. This design approach, using pulsed diode decoding and CFET inverter for NAND gates, takes less area, more stable load curve, and faster than CFET designs.